The present invention relates to semiconductor packages and systems and in particular to a semiconductor package and a system wherein necessity for mounting to a mounting board by solder is obviated.
There are conventionally known technologies for mounting a ball grid array package 10 (hereafter, abbreviated as BGA 10) over a mounting board 11 as illustrated in FIG. 1. (Refer to Patent Document 1.) In the technology disclosed in Patent Document 1, BGA 10 is comprised of a package board 13, a semiconductor element 14, a protection member 15, and a solder ball 16. The package board 13 is comprised of a core base material 17 composed of glass cloth, resin, or the like and solder resist 18 covering the upper surface and lower surface of the core base material 17 in the drawing.
An opening is provided in the solder resist 18 covering the upper surface of the core base material 17 and a bonding pad formed over the core base material 17 is exposed from this opening. This bonding pad is coupled to a wiring pattern provided in the upper surface of the core base material 17 and this wiring pattern is coupled to a via hole so provided that it penetrates the core base material 17.
The semiconductor element 14 and this bonding pad are coupled together through a bonding wire 21 and as a result, the semiconductor element 14 and the package board 13 are electrically coupled together. In the lower surface of the core base material 17, a substantially oval ball land is formed. This ball land is coupled with the above-mentioned via hole so formed that it penetrates the core base material 17 and is electrically coupled to the semiconductor element 14 through the following: the wiring pattern provided in the upper surface of the core base material 17, a bonding pad, and a bonding wire 21 bonded with this bonding pad. This ball land is exposed from an opening provided in the solder resist 18 covering the lower surface of the core base material 17. Before the BGA 10 is mounted to the mounting board 11, the solder ball 16 is placed over a ball land by a ball placer, not shown. The placed solder ball 16 is joined to the ball land by IR reflow processing or the like and the joined solder ball 16 makes an external connection terminal electrically coupled with the semiconductor element 14. The protection member 15 protects the semiconductor element 14 and the bonding wire 21.
Similarly with the package board 13, the mounting board 11 is comprised of a core base material 25 and solder resist 26 covering the upper surface and lower surface thereof in the drawing. In the upper surface of the core base material 25, there is formed an area (mounting area) where the BGA 10 is mounted. In this mounting area, there is formed a substantially oval junction land corresponding to a solder ball 16 joined to a ball land of the BGA 10. This junction land is exposed from an opening formed in the solder resist 26 covering the upper surface of the mounting board 11. The junction land is electrically coupled with some other mounted electronic component or a power supply through a wiring pattern formed in the upper surface of the mounting board 11. When the BGA 10 is mounted to the mounting board 11, the solder balls 16 of the BGA 10 are abutted against the above-mentioned junction lands provided in the mounting board 11. Subsequently, the BGA 10 and the mounting board 11 are subjected to IR reflow and as a result, the solder balls 16 are joined to the junction lands of the mounting board 11 and mounting of the BGA 10 to the mounting board 11 is completed.
Patent Document 2 discloses a technology for fixing a semiconductor package over a circuit board. In this technology, the semiconductor package is fixed over the circuit board by: passing a bolt through an insertion hole in the semiconductor package and inserting the bolt into a communication hole in the circuit board; and screwing a nut onto the tip of the bolt that penetrates the circuit board and is protruded therefrom.
Patent Document 3 discloses a non-contact power supply system using electromagnetic induction based on a printed coil.
Patent Document 4 discloses that in an electrical apparatus provided with a primary coil and a secondary coil, power is transmitted to the secondary coil in a non-contact manner by supplying a current to the primary coil.
Non-patent Document 1 discloses a technology related to measurement of 2.4 GHz RF signal quality. Non-patent Document 2 discloses a technology related to communication through an antenna using a coil.    [Patent Document 1] Japanese Unexamined Patent Publication No. 2007-12690    [Patent Document 2] Japanese Unexamined Patent Publication No. Hei 07(1995)-161865    [Patent Document 3] Japanese Unexamined Patent Publication No. 2007-157985    [Patent Document 4] Japanese Unexamined Patent Publication No. 2004-064851    [Non-patent Document 1] Koichi Nose et al., “A 0.016 mm2, 2.4 GHz RF signal Quality Measurement Macro for RF Test and Diagnosis” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 4 April 2008, pp 1038-1046    [Non-patent Document 2] Kiichi Niitsu et al., “An inductive-Coupling Link for 3D Integration of 90 nm CMOS Processor and a 65 nm CMOS SRAM” ISSCC Dig. Tech. Papers, pp. 480-482, February 2009.